Semiconductor devices are employed in various systems in a wide variety of applications. An important type of semiconductor device used as a memory is the dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). DRAM is extensively used for memory in computers. A single DRAM memory cell may include a capacitor and a transistor, each formed in a semiconductor substrate. The capacitor stores a charge representing a data value. The transistor allows the data valve to be written to the capacitor, read from the capacitor or refreshed. A series of DRAM memory cells is typically arranged in an array.
More DRAM cells can be arranged onto a semiconductor chip by reducing the surface area of the capacitor and/or the transistor thus resulting in greater memory capacity for the chip. A method of minimizing the surface area of a DRAM cell is to construct the components vertically, i.e., where a semiconductor device includes components formed in several layers. One way to accomplish such vertical construction involves forming a trench in a semiconductor substrate. For example, a dielectric film may be deposited on the sides of the trench and layers of conductive, semiconductive and/or insulative material are then deposited in the trench. Each layer may be etched so as to have a desired shape and/or size. The steps of etching and depositing new material may be repeated until the desired component, e.g., a vertical DRAM memory cell is formed.
Preferably, the capacitor is fabricated in a lower portion of the trench and at least part of the transistor is formed over the capacitor in an upper portion of the trench. The transistor may comprise source, gate and drain regions where the source is connected to a storage node of the capacitor, the drain is connected to a bit line, and the gate connected to a word line. FIG. 1 illustrates a conventional DRAM memory cell 400 including a capacitor 410 and a transistor 420. The capacitor 410 includes a first electrode 412 and a second electrode 414. Typically, a dielectric material (not shown) is disposed between the electrodes. The transistor 420 includes a source (or drain) 422 connected to the second electrode 414. The transistor 420 also includes a drain (or source) 424 connected to a bit line 432, as well as a gate 426 connected to a word line 430. The data may be refreshed, read from, or written to the capacitor 410 of each memory cell of the memory array by the bit lines 432 and the word lines 430.
As an example, the memory cell array may be arranged in rows and columns. A row may be connected to one bit line 432, and a column may be connected to one word line 430. A specific memory cell in the array is accessed by selecting the appropriate bit line 432 and word line 430. The data may be refreshed, read from, or written to the capacitor by applying appropriate voltages to the bit line 432 and/or the word line 430.
The bit line 432 may be connected to the drain (or source) 424 by a bit line contact. The word line 430 may be connected to the gate 426 by a word line contact, or the gate 426 itself may serve as the word line 430. As the surface area of the memory cell decreases, the bit line contact and the gate/word line contact may be positioned closer together. By way of example only, using current fabrication techniques, the bit line contact and the gate/word line contact may be separated by 20-30 nm. The closer positioning of the bit line contact and the gate/word line contact may cause a short circuit or induce cross-talk between the components. This problem may occur due to device fabrication errors such as misalignment, over-etching or structural defects. For example, material layers are typically patterned by depositing a masking layer over the material layer and patterning the masking layer to expose portions of the material layer which are removed while other portions are covered. Then, a new material layer may be deposited and similarly patterned. If the masking layers are misaligned with respect to one another, the upper material layer may be located incorrectly, i.e., misaligned, thereby damaging or rendering the semiconductor device inoperable. Similarly, over-etching an exposed portion of the layer may damage the material layer or another layer and may lead to a short circuit between nearby components. To prevent such short circuits or cross-talk between the bit line contact and the gate/word line contact, isolation may be employed.
A known isolation technique requires a first spacer in the trench followed in a later processing step with another spacer surrounding the gate region. The first spacer is commonly referred to as a deep trench spacer, DT top spacer or DT spacer. FIGS. 2 to 4 illustrate an example of a typical nitride spacer isolation process. As will become evident, such nitride spacer isolation may not prevent a short circuit or cross-talk in many situations.
Prior to the step illustrated in FIG. 2, a trench was formed in semiconductor substrate 100 having a surface 102. A trench top oxide (xe2x80x9cTTOxe2x80x9d) 110 was formed in a lower portion of the trench to, e.g., isolate a capacitor (not shown) within the trench from a transistor which will be formed in an upper portion of the trench. The capacitor is commonly known as a trench capacitor. A gate oxide 116 lines sidewalls 114 of the trench. On either side of the sidewalls 114 are source (drain) regions 144. Within the trench is a gate material 118 and a gate stud 130. A gate conductor 150 connects to the gate stud 130, and is protected by a silicate 172 and a nitride cap 174. A screen oxide 140 is disposed over the source (drain) regions 144. The screen oxide 140 also partly encloses a nitride spacer 142. A nitride liner 146 is formed over the screen oxide 140 and the nitride spacer 142. An array top oxide (xe2x80x9cATOxe2x80x9d) 148 is formed over the nitride liner 146. The processes of forming these elements are well known to those skilled in the art.
FIG. 2 illustrates the result of a processing step after the gate conductor 150, the silicate 172 and the nitride cap 174 have been deposited over the gate stud 130, the nitride spacer 142 and the ATO 148. The gate conductor 150, the silicate 172 and the nitride cap 174 are patterned and etched to a desired shape and size. As part of the etching process, a portion of the gate stud 130 is removed, typically by an anisotropic etch selective to oxide and nitride, leaving a recess 152 in the gate region.
After the recess 152 is formed, a gate spacer 160, also known as a gate conductor spacer or GC spacer is formed, as shown in FIG. 3. The gate spacer 160 is typically a nitride that is deposited over the wafer and covers the exposed surfaces. During deposition, the gate spacer 160 folds back on itself as it fills the recess 152. Because of the nature of the deposition process, a seam or void 162 is typically formed as well.
FIG. 4 illustrates a further fabrication step after a bit line 178 is formed. An isolating material 176, such as borophosphosilicate glass (BPSG), separates the device from other components on the wafer, such as the bit line 178. The bit line 178 connects to the source region 144 through a bit line contact 180. During processing steps such as spacer etch-back, it is difficult to maintain a uniform thickness of the gate spacer 160. Furthermore, the seam or void 162 enhances the potential for over etching the bit line contact 180, thus shorting the bit line contact 180 to the device. In particular, while the bit line etching process is typically selective to nitride, i.e., the process etches other materials more rapidly than it etches nitride, the process may rapidly etch through the seam or void 162 and provide direct contact (xe2x80x9cpunch-throughxe2x80x9d) between the bit line contact 180 and the gate material 118.
Therefore, a need exists for an improved isolation technique which provides more robust protection. The improved isolation technique of the present invention eliminates the deep trench spacer process of prior techniques. The present invention provides wider misalignment protection between the gate conductor and the trench, and avoids punch-through of the bit line contact to the device.
In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device is provided. The method includes first forming a trench having sidewalls in a semiconductor substrate. Fill material is then deposited within the trench. Then, a section of the fill material is removed to form a recess having a desired depth. Then, a spacer layer of a first material is formed to line the recess. Next, a remaining portion of the lined recess is substantially filled with a second material layer. The spacer layer and the second material layer isolate a first region of the semiconductor device from a second region of the semiconductor device. Preferably, the spacer layer is a nitride and the second material layer is an oxide.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device is provided such that a spacer and a recess fill material provide isolation between a gate material and other portions of the semiconductor device. The method includes forming a trench having sidewalls in a semiconductor substrate and forming a trench oxide within the trench. An oxide is formed along a first portion of the sidewalls between the trench oxide and an upper surface of the trench. Then, a gate material is deposited in the trench. The gate material has a surface remote from the trench oxide, and the gate material overlies the trench oxide. The gate material is partly enclosed by the gate oxide. Next, a gate conductor is deposited over the gate material. Pre-selected portions of the gate conductor and sections of the gate material are etched to form a recess having a desired depth. The recess is then lined with a spacer, which preferably comprises a nitride. The remaining portion of the recess is substantially filled with a recess fill material, which is preferably an oxide. Regardless of whether the spacer is a nitride and the recess fill material is an oxide, the spacer and the recess fill material comprise different materials.
In accordance with another embodiment of the present invention, a semiconductor device is provided, including a capacitor and a transistor. The capacitor is formed in a semiconductor substrate and the transistor is disposed adjacent to the capacitor. The transistor includes a source region electrically connected to a bit line contact, a drain region in electrical contact with the capacitor, a gate region electrically connected to a word line and a gate conductor spacer lining a portion of the gate region. The gate conductor spacer includes a recess. A recess fill material substantially fills the recess. The recess fill material has a composition different from the gate conductor spacer. The gate conductor spacer and the recess fill material are operable to prevent electrical contact between the bit line contact and the gate region.
In accordance with yet another embodiment of the present invention, a semiconductor device is provided, including a first material, a second material, a spacer material and a further material layer. The first material is formed in a semiconductor substrate and has an aperture therein. The spacer material is disposed over at least a portion of the first material, including the aperture. The spacer material does not completely fill the aperture, but leaves a recess remaining. The further material layer spans the recess and substantially fills the recess. The further material layer and the spacer material comprise different materials. The second material is partly disposed over the first material, and the spacer material and the recess-filling further material layer provide isolation between the first material and the second material. Preferably, the spacer material is a nitride and the further material layer is an oxide.